Semiconductor memory devices that store data are generally divided into volatile memory devices and nonvolatile memory devices. In a semiconductor memory device, a volatile memory device such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) etc. has the characteristic that an input/output operation of data is speedy but stored data is lost by a cut-off of power. A nonvolatile memory device such as an EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) etc. has the characteristic that an input/output operation of data is slow but stored data is maintained intact by a cut-off of power. Hence, such nonvolatile memory devices can be broadly used for memory cards for storing music or image data, or in a situation that power cannot be always supplied or a supply of power is intermittently stopped, like in a mobile phone system.
Meanwhile, particularly to overcome an integration limit of EEPROM in such nonvolatile memory devices, a demand for flash memory devices employing a 1 Tr/1 Cell structure of a batch erase system is increasing, in which data can be inputted/outputted freely electrically and which can be replaced in the future with a hard disk drive of a computer since power consumption is small and high-speed programming is valid. Such a flash memory device can be classified into a NOR type flash memory wherein two or more cell transistors are connected in parallel to a one bit line and a NAND type flash memory wherein two or more cell transistors are connected in series to a one bit line. However, in spite of the advantage that stored data is preserved even if power is cut off, such a flash memory device has a disadvantage in that operating speed is slow as compared with a volatile memory device. Thus, research for various cell structures and driving methods to increase programming and erasing speeds of flash memory devices are ongoing.
The NOR type flash memory device has a structure containing a plurality of memory cells. Each memory cell is constructed of a one bit line and a single transistor, and are connected in parallel. One memory cell transistor is connected between a drain connected to a bit line and a source connected to a common source line. The NOR type flash memory device can increase current of memory cells and can have a high speed operation. Unfortunately, high integration can be difficult because of the area occupied by a bit line contact and a source line.
Thus, in the field, a size of respective unit devices constituting a memory cell is scaled down by a trend of high integration and large capacity of a semiconductor device, and a high-integration technique to establish a multilayer structure within a limited area is also on a prosperous development, and this widely uses a laminated gate structure as one of the high-integration technique.
FIG. 1 illustrates a general laminated gate structure applied to a flash memory device.
Referring to FIG. 1, a shallow trench isolation film 12 through a general STI (Shallow Trench Isolation) process is formed on a semiconductor substrate 10 doped with P-type or N-type impurity. Then, on a channel region A of an active region defined by the STI film 12, a tunnel oxide layer 14, a floating gate 16 formed of polysilicon, a gate interlayer dielectric layer 18 constructed of an ONO (Oxide-Nitride-Oxide) layer, and a control gate 20 formed of polysilicon are formed sequentially, producing a gate region. Herewith, a tungsten silicon layer of Wsix etc. or tungsten (W) layer can be further formed on the control gate 20.
The floating gate is entirely electrically insulated from the outside under an isolated structure, and stores data by using change properties in current of a memory cell in conformity with an electron injection and electron emission to/from the floating gate. The electron injection to such floating gate employs a CHEI (Channel Hot Electron Injection) system using high-temperature electron in the channel, and the electron emission is performed through an F-N (Fowler-Nordheim) tunneling that is through use of the gate interlayer dielectric layer existing between the floating gate and the control gate. Voltage applied to the control gate is applied by a determined volume to the floating gate on the basis of a coupling ratio, and a variable deciding the coupling ratio is a capacitance of the tunnel oxide layer and a capacitance of the gate interlayer dielectric layer 18 formed of the ONO layer. In other words, an area of floating gate deciding a magnitude of the capacitance is important; an electric characteristic of flash memory device is prominent more, when thickness of a floating gate is thinner and an area of floating gate is wider.
However, in such a tendency that an integration of semiconductor device increases and a gate line width of an active region decreases, a distribution range of programming and erase voltage in a flash memory device becomes large by a distribution level through photolithography process and etching process to form a gate pattern. Furthermore, in case a thickness of floating gate becomes thicker to increase an overall area of the floating gate, there is a problem that a gap fill margin of STI film is reduced.
As a method to solve the problem an SAP (Self Aligned Poly) process is applied. But, in performing an excessive wet etch-back process in the procedure of removing a pad oxide layer in order to match with a subsequent pillar CD (Critical Dimension)(Reference Character A) in such an SAP structure, process time is lengthened and thickness of a tunnel oxide layer deposited within the pillar CD becomes different per region, which is disadvantageous in a cell distribution. Such a disadvantage is described as follows, referring to FIGS. 2A and 2B.
With reference to FIG. 2A, a pad oxide layer 102 and a nitride layer 104 are deposited sequentially on a semiconductor substrate 100 doped with P-type or N-type impurity. In a field region except an active region of the semiconductor substrate 100, an STI film 106 obtained through a general STI process is formed, wherein the STI film 106 is formed of a USG (Undoped Silicate Glass) film.
With reference to FIG. 2B, the nitride layer 104 (FIG. 2A) is etched by using, e.g., HF and phosphorus acid, in the semiconductor substrate on which the STI film 106 is formed. Then, the pad oxide layer 102 (FIG. 2A) is removed by using, e.g., HF, and next, a tunnel oxide layer 108 is deposited to form a laminated gate.
Herewith, in using the HF as etchant, the pad oxide layer 102 (FIG. 2A) is etched, and simultaneously, the USG film as the STI film 106 is etched. At this time, an excessive wet etch-back process on the STI film 106 is essential to ensure a pillar CD for the SAP structure. The pillar CD can be ensured for a desired size through an excessive etch-back process, but process time is lengthened by the excessive etching, and also a sinking effect (Reference Character B) is caused in a portion of the semiconductor substrate 100 contacted with the STI film 106, as illustrated. Also, a surface flatness of the active region is not uniform. As its result, on a center region of the pillar CD shown in reference character C and an edge region of the pillar CD shown in reference character D, deposition thickness of the tunnel oxide layer 108 becomes non-uniform. Unfortunately, when deposition thickness of the tunnel oxide layer is not uniform, a cell distribution is not good and the electrical characteristic of a memory device is degraded, thereby lowering reliability. Further, excessive wet etch-back to ensure the pillar CD delays processing, thus lowering productivity.